VLSI Implementation of Reconfigurable FFT Processor Using Vedic Mathematics
DOI:
https://doi.org/10.51611/iars.irj.v5i2.2015.48Keywords:
Bit parallel multiplier, Complex Multiplier, FFT, Vedic MathematicsAbstract
Fast Fourier transform has been used in wide range of applications such as digital signal processing and wireless communications. In this we present a implementation of reconfigurable FFT processor using single path delay feedback architecture. To eliminate the use of read only memory’s (ROM’S). These are used to store the twiddle factors. To achieve the ROM-less FFT processor the proposed architecture applies the bit parallel multipliers and reconfigurable complex multipliers, thus consuming less power. The proposed architecture, Reconfigurable FFT processor based on Vedic mathematics is designed, simulated and implemented using VIRTEX-5 FPGA. Urdhva Triyakbhyam algorithm is an ancient Vedic mathematic sutra, which is used to achieve the high performance. This reconfigurable DIF-FFT is having the high speed and small area as compared with other conventional DIF-FFT
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References
Bi Guoan and E.V.Jones, (1989). “A pipelined FFT processor for word sequential Data,†IEEE transaction on acoustics, speech, and signal processing, vol.37, no.12.
Chu Yu, Mao-Hsu Yen, Pao-Ann Hsiung, and Sao-Jie Chen, (2011). “A low- power 64-point pipeline FFT/IFFT processor for OFDM applicationsâ€, IEEE transactions on consumer electronics, vol.57, no.1.
Cooley.J.W and Tukey. J.W, (1965). “An algorithm for the machine calculation of complex Fourier series,†Math computational, vol.19, pp.297-301.
Hasan.M, Arslan.T and Thompson.J.S, (2003). “A novel coefficient ordering based low power pipelined Radix-4 FFT processor for wireless LAN applications,†IEEE Transaction on consumer Electronics, vol.49, no.1.
Hasan.M and Arslan.T, (2003). “Implementation of low power FFT processor cores using a novel order based processing schemeâ€, accepted for publication in IEE proceedings on circuits, Devices and systems.
He.S and Torkelson.M, (1998). “Design and implementation of a 1024-point pipeline FFT processor,†in Proc. IEEE Custom Integrated Circuits Conf. (CICC’98), pp. 131–134.
Jen-chi Kuo, Ching-Hua Wen, Chih-Hisu Lin, and An-Yeu wu, (2003) “VLSI design of a variable length FFT/IFFT processor for OFDM based communication system,†EURASIP journal on applied signal processing, no.13.pp.1306-1316.
Jung.Y, Yoon.H and Kim.J, (20030 “New efficient FFT algorithm and pipeline implementation results for OFDM/DMT applications,†IEEE transaction on consumer electronics, vol.49, no.1, pp.14-20.
Lin Y-M, Liu H-Y, and Lee C-Y, (2005). “A 1 GS/s FFT/IFFT processor for UWB applications,’’ IEEE journal of solid-state circiuts, vol.40, no.8, pp.1726-1735.
Parthi. K.K, (1999) VLSI Digital signal processing systems: Design and Implementation, New York: Jon Wiley and sons.
Sarada.V, Vigneswaran.T, (2013). “Reconfigurable FFT processor,†International Journal of Engineering and Technology, vol.5, no.2.
Sri Sathya Sai Veda Pratistan “Vedic Mathematicsâ€, Book.
Wei Han.T. Arsan, Erdogan.a.t, Hasan.m, (2004). “A novel low power pipelined FFT based on sub expression sharing for wireless LAN applications,†IEEE workshop on signal processing systems, pp.83-88.
Wen-Chang Yeh and Chein-Wei Jen, (2003). “High-speed and low power split-radix FFT,†IEEE Transaction on signal processing, vol.51, no.3, pp.864-874.
Zhong. G, Xu.F and Wilson. A.N, (2006). “A power-scalable reconfigurable FFT/IFFT IC based on multiprocessor ring,†IEEE solid-state circuits, vol.41, no.2, pp.483-495
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Copyright (c) 2015 Bharatha K. Babu, G. Nanthini
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