BABU, Bharatha K.; NANTHINI, G. VLSI Implementation of Reconfigurable FFT Processor Using Vedic Mathematics. IARS’ International Research Journal, Victoria, Australia, v. 5, n. 2, 2015. DOI: 10.51611/iars.irj.v5i2.2015.48. Disponível em: https://researth.iars.info/index.php/curie/article/view/48.. Acesso em: 22 nov. 2024.